1. Field of the Invention
The present invention relates to testing electronic components such as discrete, analog components, and more specifically, is directed to methods and apparatus for acquiring and graphically displaying component test data, and for ensuring validity of the displayed data.
2. Background
In the prior art, measuring current-voltage (I-V) characteristics of a component requires the voltage across the device under test (DUT) and the current through the DUT for each point in time. To do so, both current and voltage traditionally are measured simultaneously as a stimulus signal is applied to the DUT.
An improved component test method and apparatus for implementing the method are disclosed in commonly-assigned U.S. patent application entitled "Direct Digital Synthesis Component Test," Ser. No. 08/289,752, filed Aug. 11, 1994. According to that application, separate voltage and current scans are triggered at the same point in time and phase relative to a periodic start time. The start time preferably is the beginning of a cycle of a digitally synthesized test stimulus signal. Said patent application is incorporated herein by this reference.
When a test instrument of the type disclosed in the aforementioned application is switched to a component test mode of operation, a measurement scan, e.g. a voltage scan, begins immediately. Measurement data is acquired and stored beginning on the next trigger point. However, if a probe is applied during the scan, the acquired scan data, and hence the resulting visual display, will be inaccurate. This problem appears if the probes are placed during either the voltage or the current scan.
Another problem can arise upon entering component test mode. Assume that a test instrument is switched to the component test mode and a "Hold" function is enabled. The instrument would "hold" an invalid state (open circuit) if the probes are applied after the instrument is switched to component test. There would be no valid data to display, but the invalid display would be "held".
A further problem related to entering component test mode is time delay before valid component test data is available for display. In a test instrument that digitally synthesizes a test stimulus waveform, the stimulus frequency can be very low or near DC, e.g. 2 Hz. Accordingly, it can take at least several seconds before valid scan data are acquired and displayed. In the meantime, a user may be unsure whether the instrument is operating properly; or, the user may incorrectly infer from an invalid display that the device under test (DUT) is defective. Accordingly, there is a need to defer displaying component test data until such data is known to be valid.
Another problem arises if a user removes a probe during a component test scan. Again, the data acquired during that scan will be invalid. And, if a graphic display of component test data is in use, e.g. a Lissajous pattern, the resulting pattern is likely to be dramatically distorted and perhaps unrecognizable. Such a result is disconcerting to the user and may be misinterpreted as an indication of a failure in the test instrument.
A related problem is illustrated by first assuming that the test instrument is operating with a "Hold" function enabled. A user places the probes on the DUT long enough to recognize the component as present, to do a voltage scan, and to start a current scan. Then the user removes the probe from the component, thereby interrupting the current scan. Actually, the current scan will be completed in any event but the most recent current measurement values will be zero. Again, the resulting graphic display will be distorted and misleading. The need remains therefore to acquire and display component test data that are accurate and logical, both when entering and throughout component test operations.